题目/Title：An FPGA Emulation Platform for Polar Codes

作者/Author：
                        Chenrong Xiong,Yi Zhong,Chun Zhang,Zhiyuan Yan

会议/Conference：SiPS 2016

地点/Location：Dallas, TX, USA

年份/Issue Date：2016.26-28 Oct.

页码/pages：pp. 148 - 153

摘要/Abstract：
Both fiber optical communication and data storage applications have a stringent requirement for the bit error rate (BER) as low as 10 12 to 10 15. As a promising candidate of future error correcting codes, it is very time consuming, or even infeasible, to evaluate the BER performance of polar codes at such a low level with the software Monte-Carlo simulation. In this paper, we proposed an FPGA test plat form to tackle this problem. In this platform, the encoder, the channel model, and the decoder are implemented. Furthermore, an embedded CPU and an AXI interface are integrated as well to configure our design to test error performance of different codes without re- implementing the decoder. Furthermore, our decoder design has a multi-mode feature which provides a way to test the error performance of CA-SCL algorithms with different list sizes.