题目/Title：Data lane design for transmitter of 4.8Gbps serdes in 65nm CMOS

作者/Author：
                        Peng Wang,Ziqiang Wang,Chun Zhang,Zhihua Wang

会议/Conference：EDSSC 2014

地点/Location：Chengdu, China

年份/Issue Date：2014.18-20 Jun.

页码/pages：pp. 1 - 2

摘要/Abstract：
This paper presents a data lane circuit for transmitter of 4.8Gbps serdes in 65nm CMOS process. The data lane circuit mainly consists of 32:1 multiplexer (MUX) and equalizer. MUX adopts half-rate architecture and CMOS circuits to relax clock requirement and save power. The equalizer is a 4-tap feed forward equalizer (FFE) that can operate at two driving modes. Measurement shows that FFE can compensate over 7 dB channel loss at 4.8Gbps. And comparison of two modes is presented as design reference. The circuit's area is 230×350 μm2.