题目/Title：基于65nm CMOS用于导航接收机的2mW 50dB范围宽带混合AGC设计
                        A 2-mW 50-dB DR wideband hybrid AGC for a GNSS receiver in 65 nm CMOS

作者/Author：续阳,池保勇,徐阳,祁楠,王志华
                        Yang Xu,Baoyong Chi,Yang Xu,Nan Qi,Zhihua Wang

期刊/Journal：半导体学报 Chinese Journal of Semiconductors

年份/Issue Date：2012.Jul.

卷（期）及页码/Volume（No.）&pages：Vol.33, No.7, pp. 075006 - 1 - 8

摘要/Abstract：
实现了一种用于导航接收机的低功耗宽带混合自动增益控制(AGC)环路。I/Q路中单个AGC由四级可编程增益放大器(PGAs)、差分峰值检测、两个比较器、控制算法逻辑、译码器和参考电压源组成。除了能由AGC环路控制外，PGA的增益也能通过SPI接口由片外数字基带处理器控制。为获得低功耗和噪声，采用一种改进的源简并放大器，且I/Q路间的相位失配能以0.2º精度在±5º范围内校准。整体电路用65nm CMOS实现，测试的PGA总增益为9.8dB~59.5dB，平均步进为0.95dB，且仿真带宽超过110MHz。从
A low-power wideband hybrid automatic gain control (AGC) loop for a GNSS receiver is presented. Single AGC in the I/Q path is composed of four-stage programmable gain amplifiers (PGAs), a differential peak detector, two comparators, control algorithm logic, a decoder and the reference voltage source. Besides being controlled by AGC loop, the gain of PGAs could be alternatively controlled by off-chip digital baseband processor through SPI interface. To obtain low power consumption and noise, an improved source degenerated amplifier is adopted, and the I/Q path phase mismatch within ±5º range is calibrated with 0.2º accuracy. Implemented in 65nm CMOS, the measured PGAs total gains range from 9.8dB to 59.5dB with an average step of 0.95dB and simulated bandwidth of more than 110MHz. The settling time is about 180μs with 80% AM input with measured signal power from -76.7dBm to -56.6dBm from radio-frequency amplifier (RFA) input port, and also reduces to 90μs with clock frequency doubling. The single AGC consumes almost 0.8mA current from the 2.5-V supply and occupies an area of 750×300μm2.