题目/Title：VLSI architecture of EBCOT tier-2 encoder for JPEG2000

作者/Author：
                        Leibo Liu,Ning Chen,Li Zhang,Zhihua Wang

会议/Conference：ASICON 2005

地点/Location：Shanghai, China

年份/Issue Date：2005.24-27 Oct.

页码/pages：pp. 173 - 176

摘要/Abstract：
This paper proposed a VLSI architecture of embedded block coding with optimized truncation (EBCOT) tier-2 encoder for JPEG2000. Based on a rate-distortion (RD) slope method, the proposed architecture eliminate the iteration of the RD truncation, reduces the scale of the on-chip bit-stream buffering from full tile size down to three-code-block size and at the same time, accurately control the compression bit-rate with 95% precision. The proposed tier-2 encoder has already been integrated into the JPEG2000 codec and fabricated with SMIC 0.18mum 1P6M CMOS technology