Title：Design method of fully-customized low-leakage digital circuit standard unit

Country：China

Patent No.：202010301436.X

Legal Status：Authorized

Inventor：Hanjun Jiang, Yue Yin, Zhihua Wang, Chun Zhang

Assignee：Tsinghua University

Address：Tsinghua University,Haidian District Beijing 100084, China

Filing Date：2020-04-16

Issue Date：2022-12-27

The invention discloses a design method of a fully-customized low-leakage digital circuit standard unit, and the method comprises the steps: in circuit design, employing a transistor with a short channel width and a large channel length in circuit design, so as to increase the on-resistance of a digital circuit standard unit circuit, and restrain the barrier reduction effect of a drain end induction source end; and suppressing charge and discharge of a transistor gate capacitor by adopting a mode of connecting a substrate with a large resistor and independently biasing; in layout design, enabling unit layout fixed height, the N trap and the substrate to adopt variable dynamic heights; and cancelling the filling unit, adding a substrate and N trap contact in each unit layout to avoid the latch-up effect caused by size increase and layout and wiring; and fully utilizing the area space. The invention further provides a bottom layer metal wiring gap debugging method. Based on a deep submicron/nanoscale CMOS integrated circuit manufacturing process, the designed digital circuit standard unit has good static electricity leakage performance, basic functions of each unit circuit provided by an original process library can be realized, and the digital circuit standard unit can be used for a comprehensive full-custom digital large-scale integrated circuit.

Patent Certificate： PDF/Jpg