Title：A bit synchronization circuit for zero IF GFSK demodulator
Country：China
Patent No.：201510325627.9
Legal Status：Authorized
Inventor：Hong Chen, Guanghua Wu, Yanyi Meng
Assignee：Tsinghua University
Address：Mailbox No. 82, Beijing 100084
Filing Date：2015-06-12
Issue Date：2017-05-17
Abstract：
The invention proposes a bit synchronization circuit for a zero-intermediate-frequency GFSK demodulator. A shift register module is used to store a sampling value; a correlation value calculation module is used to calculate the correlation values of two signals; a correlation value accumulation module is used to calculate the sum of the correlation values; a comparator module is used to obtain a bit synchronization signal pulse; and finally, a delayer module is used to delay the pulse by a period of time to obtain a final correct bit synchronization signal. The bit synchronization circuit is applicable to a GFSK modulation signal of a lead code in which 0101 appears alternately, and the modulation coefficient is large. The theoretical basis is that the GFSK modulation signal of the lead code in which 0101 appears alternately is of bilateral symmetry, and the axis of symmetry is just the code element end moment. The bit synchronization circuit has the advantages of simple structure and accurate synchronization.
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