Title：An on-chip aiding testing system and method of ΔΣ ADC
Country：China
Patent No.：201110115373.X
Legal Status：Authorized
Inventor：Yafei Ye, Liyuan Liu, Dongmei Li
Assignee：Tsinghua University
Address：Tsinghua University,Haidian District Beijing 100084, China
Filing Date：2011-05-05
Issue Date：2013-05-01
Abstract：
The invention relates to an on-chip auxiliary testing system of a delta-sigma analog-digital converter and an auxiliary testing method of the same. The on-chip auxiliary testing system comprises a memory module, a parallel port/serial port module and a control scheduling module integrated on the chip of the delta-sigma analog-digital converter; wherein one digital output end of the memory module is connected with the digital input end of the parallel port/serial port module, and the control signal output end of the control scheduling module is respectively connected with the control signal input ends of the memory module and the control scheduling module; and the control ends of the memory module and the control scheduling module are respectively used for receiving signals of the delta-sigma analog-digital converter. The auxiliary testing method comprises two auxiliary testing modes. When the device is used, no load is introduced into the PAD (pure audio design) for testing during operation of the delta-sigma analog-digital converter, the delta-sigma analog-digital converter stops operating when the performance of the chip is tested, the operation and testing of the delta-sigma analog-digital converter are separated, and the influence of the external testing environment on the operation of the chip can be minimized.
Patent Certificate：
PDF/Jpg