题目/Title：一种高能效基4-Booth编码并行乘法器设计
An energy efficient radix-4 Booth encoding parallel multiplier design
作者/Author：黄焘，闰闰，胡毅，尹立，谢翔
Tao Huang, Run Run, Yi Hu, Li Yin , Xiang Xie
期刊/Journal：电子技术应用
年份/Issue Date：2023.Apr.
卷（期）及页码/Volume（No.）&pages：Vol.49, No.4, pp.117-122
摘要/Abstract：
常用的卷积神经网络中存在数十亿次乘法运算，神经网络中乘法的大量能耗成为硬件实现神经网络的能效瓶颈之一。为了降低乘法器的能耗，提出了一种高能效基4-Booth编码并行乘法器。通过改进部分积生成模块，消除了传统方法中的补偿位，使得乘法器延时减小且能耗降低。后仿真结果显示，所提出的乘法器比现有乘法器面积减小了5.2%，延时减小了6.3%，能耗降低了10.8%。
Common-used Convolutional Neural Networks (CNNs) contain billions of multiplications, which is the bottleneck of hardware implementation of CNNs. To reduce energy cost of multiplier, an energy-efficient radix-4 Booth encoder multiplier is proposed. By improving the partial product module, the compensation bits in conventional multipliers are eliminated, which reduces the delay and energy cost of multiplier. Post simulation indicates that the proposed multiplier reduces the area, delay and energy cost by 5.2%, 6.3% and 10.8% respectively. The proposed multiplier can be used in neural network accelerators and breaks the energy efficiency bottleneck.