题目/Title：A 4.8-GHz Time-Interleaved Multi-Reference PLL with 16.1-fs Jitter
作者/Author：
Hongzhuo Liu, Wei Deng, Haikun Jia, Shiwei Zhang, Shiyan Sun, Baoyong Chi
会议/Conference：ESSCIRC 2023
地点/Location：Lisbon, Portugal
年份/Issue Date：2023.11-14 Sept.
页码/pages：pp.261-264
摘要/Abstract：
This paper presents a 4.8-to-5.6 GHz timeinterleaved multi-reference PLL with sub-20fs jitter. The reference clocks are aligned with the time-interleaved feedback clocks produced by the multi-phase divider. Fabricated in 65-nm CMOS technology, the prototype achieves 16.1-fs jitter integrated from 10kHz to 40MHz at 4.8-GHz carrier, and consumes 83mW. To the best knowledge of the authors, it is the lowest jitter PLL in CMOS/SiGe technology reported so far.