题目/Title：A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase Noise +20logNdiv

作者/Author：
                        Hongzhuo Liu, Wei Deng, Haikun Jia, Shiyan Sun, Qixiu Wu, Jiajie Tang, Zhihua Wang, Baoyong Chi

会议/Conference：ESSCIRC 2022

地点/Location：Milan, Italy

年份/Issue Date：2022.19-22 Sept.

页码/pages：pp.233-236

This paper presents a PLL using synchronized multiple references with in-band phase noise (PN) lower than the conventional theoretical limit of reference phase noise+20logNdiv . The proposed technique provides design flexibility to alleviate the jitter-power trade-off in PLL. Realized in 65-nm CMOS, the prototype achieves in-band PN 1.7-dB lower than the conventional theoretical limit, with four synchronized references. The proposed PLL can be configured in a single reference mode achieving 0.54-ps integrated jitter. In the contrast, the proposed PLL using four synchronized references achieves 0.35-ps integrated jitter.