题目/Title：A 1Mb/s 2.86% EVM GFSK Modulator Based on ΔΣ BB-DPLL without Background Digital Calibration

作者/Author：
                        Yuguang Liu,Woogeun Rhee,Zhihua Wang

会议/Conference：RFIC 2020

地点/Location：Los Angeles, CA, USA

年份/Issue Date：2020.4-6 Aug.

页码/pages：pp. 7 - 10

摘要/Abstract：
This paper presents a two-point modulation architecture based on the 螖危 bang-bang digital PLL (BB-DPLL) that does not rely on high-resolution digital-to-time converter (DTC) to avoid long digital calibration time for wireless systems. Multiple techniques are integrated to improve in-band noise performance and overcome DCO nonlinearity. In the proposed two-point modulator, FIR-filtered 1b high-pass modulation overcomes the nonlinearity of a digitally-controlled oscillator (DCO), while low-pass modulation achieving good linearity with a 1b time-to-digital converter (TDC) having high reference frequency. To mitigate in-band noise degradation in the 螖危 BB-DPLL, a third-order 螖危 modulator with a 1b output, a 4b hybrid DTC using a 3b delay line and a 1b phase-interpolated frequency divider, and a 螖危 BB-DPLL with high reference frequency are employed. A prototype 1.8GHz 1Mb/s GFSK modulator implemented in 65nm CMOS achieves the in-band phase noise of -94dBc/Hz and the EVM performance of 2.86%, while consuming 5.3mW from a 1V supply.