题目/Title：用于植入式心电监测的12位低功耗SAR ADC
                        A 12 bit Low Power SAR ADC for Implantable ECG Monitoring

作者/Author：王冰,姜汉钧,郭衍束,王志华
                        Bing Wang,Hanjun Jiang,Yanshu Guo,Zhihua Wang

期刊/Journal：微电子学 Microelectronics

年份/Issue Date：2019.Dec.

卷（期）及页码/Volume（No.）&pages：Vol.48, No.6, pp. 728 - 732+737

摘要/Abstract：
设计并实现了一个用于植入式心电监测的12位低功耗逐次逼近型模数转换器(SAR ADC)。针对低功耗的应用需求,提出了一种静态预放大比较器与动态预放大比较器分时工作的时分比较方案,在保证比较精度的基础上实现了低功耗。针对低采样率时的漏电问题,采用了异步自控制逻辑、双电源电压供电和晶体管的最小栅长堆叠等方法,降低了漏电功耗。设计的ADC采用65nm CMOS工艺实现。仿真结果表明,采样率为1kS/s时,信噪失真比SNDR在各工艺角下均不小于69.9dB,有效位数为11.3位,功耗仅为30nW,漏电功耗占总功耗
An ultra-low power 12-bit successive-approximation register (SAR) ADC was designed for implantable electrocardiography (ECG) monitoring. In order to meet the requirements of low power consumption, a time-division comparison scheme with static pre-amplification comparators and dynamic pre-amplification comparators working at different timing was proposed. Low power was achieved on the basis of satisfying the comparison accuracy by the proposed scheme. In addition, the techniques such as asynchronous self-controlled logic operating, dual-voltage power supplying and transistors minimum gate length stacking were utilized to reduce the leakage current. This ADC was implemented in a 65 nm CMOS process. The simulation results showed that, at a sampling rate of 1 kS/s, the SNDR was more than 69.9 dB at different corners, the corresponding effective number of bit (ENOB) was 11.3 bit, and the power consumption was only 30 nW. The leakage consumption occupied 11% of the total power consumption. Thus the figure-of-merit (FoM) was 11.8 fJ/(conv·step).