题目/Title：A ΔΣ DPLL with 1b TDC, 4b DTC and 8-tap FIR filter for low-voltage clock generation/modulation systems

作者/Author：
                        Xiaohua Huang,Han Liu,Woogeun Rhee,Zhihua Wang

会议/Conference：VLSI-DAT 2018

地点/Location：Hsinchu, Taiwan

年份/Issue Date：2018.16-19 April

页码/pages：pp. 1 - 4

摘要/Abstract：
This paper describes a low-complexity digital-intensive in-band noise and out-of-band noise reduction method for 螖危 fractional-N bang-bang digital PLLs (BB-DPLLs). The use of only a 4b digital-to-time converter (DTC) with auto-tuned delay cells provides a moderate way to mitigate the phase folding effect in the fractional-N BB-DPLL for decent in-band noise performance. An 8-tap hybrid finite-impulse response (FIR) filter is also utilized to suppress the out-of-band noise caused by the 螖危 modulation in a wideband PLL. A prototype 螖危 BB-DPLL is implemented in 65nm CMOS. Experimental results show that the proposed methods reduce the in-band phase noise by about 11dB and both the out-of-band noise and the fractional spurs by about l8dB with the maximum linearity requirements of 4b and 3b for the DTC and the FIR filter.