题目/Title：一种带低功耗参考电压缓冲器的11位、200MS/s的 Subrange SAR ADC
                        An 11-bit 200MS/s Subrange SAR ADC with Low-Cost Integrated Reference Buffer

作者/Author：何秀菊,谷宪,李玮韬,姜汉钧,李福乐,王志华
                        Xiuju He,Xian Gu,Weitao Li,Hanjun Jiang,Fule Li,Zhihua Wang

期刊/Journal：半导体学报 Journal of Semiconductors

年份/Issue Date：2017.Oct.

卷（期）及页码/Volume（No.）&pages：Vol.38, No.10, pp. 88-93

摘要/Abstract：
论文中介绍了一款带参考电压缓冲器的11位、200MS/s Subrange SAR ADC，此芯片已在65nm CMOS工艺成功流片并测试。此ADC采用了3.5bit的Flash ADC进行粗转换。为了提升转换速度，在flash/SAR交界处采用了紧凑的时序设计。然后，Flash ADC的转换结果控制电荷补偿电路工作，以降低参考电压与输入信号相关的电压波动。测试结果表明，采用对参考电压的电荷补偿电路之后，ADC性能得到了明显提升。此外，采样率为200MS/s时，信号噪声失真比可达到59.5dB。在1.2V
This paper presents an 11-bit 200 MS/s subrange SAR ADC with an integrated reference buffer in 65 nm CMOS. The proposed ADC employs a 3.5-bit flash ADC for coarse conversion, and a compact timing scheme at the flash/SAR boundary to speed up the conversion. The flash decision is used to control charge compensating for the reference voltage to reduce its input-dependent fluctuation. Measurement results show that the fabricated ADC has achieved significant improvement by applying the reference charge compensation. In addition, the ADC achieves a maximum signal-to-noise-and-distortion ratio of 59.5 dB at 200 MS/s. It consumes 3.91mW from 1.2V supply, including the reference buffer.