题目/Title：应用于 CMOS 图像传感器的 Pipelined SAR模数转换器设计
                        Design of a Pipelined SAR ADC Used in CMOS Image Sensor

作者/Author：李臻,李冬梅
                        Zhen Li,Dongmei Li

期刊/Journal：微电子学与计算机 Microelectronics & Computer

年份/Issue Date：2016.Nov.

卷（期）及页码/Volume（No.）&pages：Vol.33, No.11, pp. 64 - 68

摘要/Abstract：
本论文设计实现一种应用于 CMOS 图像传感器的 10bit 模数转换器（ ADC）， 采用基于逐次逼近的新型流水线结构（ Pipelined SAR ADC）。 提出了一种优化选取其中高精度倍增数模转换器（ MDAC）和单位电容值的解析方法。通过采用第一级高精度、半增益 MDAC 和动态比较器等技术提高了整体电路的线性度， 并降低了系统功耗。 通过对版图面积的优化设计，满足了 CMOS 图像传感器对芯片面积的要求。 本设计基于 180nm CMOS 工艺， 仿真结果显示电路实现了 60.37dB 的信噪
This paper presents a novel architecture to achieve a 10bit pipeline ADC based on SAR technique which is used in a CMOS image sensor. A theoretical analysis is proposed to determine the high resolution MDAC and the suitable value of unit capacitor. The high-resolution first stage, the half-gain MDAC and the dynamic comparator are adopted to improve the linearity and to reduce the power. To satisfy the strict area requirement of CMOS image sensor, the layout is carefully designed. This pipelined SAR ADC is designed and fabricated in SMIC 180nm CMOS technology. Simulation results show the ADC achieves 60.37dB signal to noise distortion ratio (SNDR) and 76.37dB spurious free dynamic range（ SFDR） . The effective number of bits (ENOB) achieves 9.74 bit. The core area is 140umⅹ280um, about 0.04 mm2. The power dissipation is 9.8mW in typical case under 2.8V supply.