题目/Title：DDR2 SDRAM控制器IP功能测试与FPGA验证
                        The Function Simulation of DDR2 SDRAM Controller IP and Verification in FPGA

作者/Author：陈平,张春,张一山,姜汉钧,王志华
                        Ping Chen,Chun Zhang,Yishan Zhang,Hanjun Jiang,Zhihua Wang

期刊/Journal：微电子学 Microelectronics

年份/Issue Date：2016.Apr.

卷（期）及页码/Volume（No.）&pages：Vol.46, No.2, pp. 251 - 254

摘要/Abstract：
完成挂载在AHB上对DDR2 SDRAM进行操作的DDR2控制器IP模块设计并通过相关读写测试。然后利用Altera的Qsys平台，将得到的DDR2控制器IP挂载到NiosII上，搭建SoPC系统，完成软硬件协同验证。验证结果表明该IP在StratixIV的FPGA核心芯片共占用287个逻辑单元，DDR2的工作频率可达200MHz。同时，开发出了一套通用的将AHB总线接口的IP挂载到NiosII的Avalon总线上进行FPGA验证的方法。
The DDR2 controller module was extracted from LEON3 open-source processor. Relevant read and write tests were accomplished. Moreover, the DDR2 controller IP was connected to NiosII CPU based on Altera’s Qsys platform .The SoPC system completed hardware and software co-verification. Results showed that 287 ALUTs of StratixIV FPGA core chip were occupied and the DDR2 SDRAM operating frequency was up to 200MHz. Meanwhile, a set of method was developed to connect IP with AHB bus interface to NiosII’s Avalon bus and complete the FPGA verification.