题目/Title：An 11-bit 250MS/s subrange-SAR ADC in 40nm CMOS

作者/Author：魏舒舒,谷宪,李福乐,王志华
                        Shushu Wei,Xian Gu,Fule Li,Zhihua Wang

会议/Conference：ISNE 2016

地点/Location：Hsinchu, Taiwan

年份/Issue Date：2016.3-6 May

页码/pages：pp. 1 - 2

摘要/Abstract：
The subrange SAR ADC in this paper consists of coarse conversions of 4-bit flash ADC and fine conversions of 8-bit SAR ADC, which fully combines high speed of flash ADC and low power consumption of SAR ADC. The design is fabricated in a 40nm low-leakage process, and the core area is 0.018mm. The post layout simulation achieves an ENOB of 9.99 bits at Nyquist input and consumes 1.5mW from 1.1V supply, leading This paper presents an 11-bit 250MS/s subrange SAR ADC. The subrange SAR ADC in this paper consists of coarse conversions of 4-bit flash ADC and fine conversions of 8-bit SAR ADC, which fully combines high speed of flash ADC and low power consumption of SAR ADC. The design is fabricated in a 40nm low-leakage process, and the core area is 0.018mm . The post layout simulation achieves an ENOB of 9.99 bits at Nyquist input and consumes 1.5mW from 1.1V supply, leading to a FOM of 5.86fJ/conv-step.