题目/Title：一种低功耗11位100MS/s采样率SAR ADC IP
                        A low power 11-bit 100MS/s SAR ADC IP

作者/Author：王亚,薛春莹,李福乐,张春,王志华
                        Ya Wang,Chunying Xue,Fule Li,Chun Zhang,Zhihua Wang

期刊/Journal：半导体学报 Journal of Semiconductors

年份/Issue Date：2015.Feb.

卷（期）及页码/Volume（No.）&pages：Vol.36, No.2, pp. 025003-5

摘要/Abstract：
本文介绍了一种双通道11位100MS/s采样率的混合结构SAR ADC IP。每个通道均采用flash-SAR结构以达到高速低功耗的目的。为了进一步降低功耗，flash和SAR中的比较器均采用全动态比较器。SAR中逐次逼近逻辑所需要的高速异步触发时钟采用门控环形振荡器产生。为了提高电容的匹配性，在版图设计中，采用底板包围顶板的MOM电容结构，有效减小电容寄生。本设计制造工艺为SMIC55nm的低漏电CMOS工艺，双通道的总面积为0.35mm2且核心面积仅为0.046 mm2。双通道模数转换器在1.2V供
This paper presents a dual-channel 11-bit 100MS/s hybrid SAR ADC IP. Each channel adopts flash-SAR architecture for high speed, low power and high linearity. Dynamic comparators in the coarse flash ADC and the fine SAR ADC further contribute to the reduction of power consumption. A gate-controlled ring oscillator generates a multi-phase clock for SAR logic, thereby allowing it asynchronously triggers the comparator in the fine SAR ADC in high speed. MOM capacitors with fully shielded structure provide enough matching accuracy without the need for calibration. This design was fabricated in SMIC 55nm low leakage CMOS technology and the active area of dual-channel (I-Q) ADC is 0.35mm2, the core area is 0.046 mm2. It consumes 2.92mA at 1.2V supply, for dual-channel too. The effective number of bits (ENOB) is 9.90 bit at 2.4MHz input frequency, and 9.34 bit at 50MHz. Leading to a FOM of 18.3 fJ/conversion-step