题目/Title：A 0.55V 100MHz ADPLL with ΔΣ LDO and Relaxation DCO in 65nm CMOS

作者/Author：
                        Yudong Zhang,Woogeun Rhee,Zhihua Wang,Taeik Kim,Hojin Park

会议/Conference：RFIT 2015

地点/Location：Sendai, Japan

年份/Issue Date：2015.26-28 Aug.

页码/pages：pp. 190 - 192

摘要/Abstract：
A 0.55V 100MHz LDO-embedded ADPLL is implemented in 65nm CMOS. A digitally-controlled relaxation oscillator (DCRXO) with a variable-threshold inverter and a digital calibration circuit is designed for robust start up under ultra-low supply voltage. A ΔΣ modulated pseudo-digital LDO provides a PVT-insensitive dithered internal voltage for the DCRXO. The 100MHz ADPLL including the LDO consumes a 67??W from a 0.55V supply and achieves the phase noise of ???82.9dBc/Hz at 1MHz offset frequency. The LDO achieves >20dB PSRR when sinusoidal noise is injected to the supply.