题目/Title：一种高速宽带连续时间Delta-Sigma调制器设计
                        Design of a High-speed Wide-band Continuous-Time Delta-Sigma Modulator

作者/Author：王轶彬,韩晨曦,李冬梅
                        Yibin Wang,Chenxi Li,Dongmei Li

期刊/Journal：微电子学与计算机 Microelectronics & Computer

年份/Issue Date：2014.Dec.

卷（期）及页码/Volume（No.）&pages：Vol.31, No.12, pp. 93 - 97

摘要/Abstract：
利用MATLAB SIMULINK工具设计了一款高速连续时间Delta-Sigma调制器。该调制器采用单环3阶4位量化带前馈结构，设计指标为14位精度、2MHz信号带宽。通过对积分器运放有限直流增益（DC gain）、积分器运放有限增益带宽积(GBW)、额外环路延时（ELD）等电路非理想因素进行建模，确定各非理想因素边界范围并提供电路级各模块设计指标。在UMC 180nm工艺下进行电路、版图设计及流片实现。量化器中设计采用了一款高速、高精度、低噪声、带预放大级的动态锁存比较器。调制器中采用一种低延时的动态
This paper presents a high-speed wide-band continuous-time (CT) Delta-Sigma (ΔΣ) modulator. The modulator is modeled in MATLAB SIMULINK with a single-loop 3rd-order 4-bit quantization structure. By modeling non-ideal factors such as limited OPAMP DC gain, limited gain bandwidth product (GBW) and excess loop delay (ELD), design properties of circuit module are determined. The modulator is designed and implemented in UMC 180nm process. High-speed dynamic latch comparator with low-noise and high-resolution is designed for quantization. Dynamic element matching (DEM) module with low latency is included to suppress DAC mismatching. A direct feedforward path is introduced by RPI to compensate for excess loop delay (ELD). The modulator achieves a pre-layout 83dB signal to noise distortion ratio (SNDR) with a figure of merit (FOM) of 220fJ/conv-step and occupies 0.1mm2 active area.