题目/Title：适用于编译器的高速SRAM阵列及外围设计
                        Design of High-Speed SRAM Array and Periphery for Compiler

作者/Author：曹华敏,刘鸣,陈虹,郑翔,王聪,王志华
                        Huamin Cao,Ming Liu,Hong Chen,Xiang Zheng,Cong Wang,Zhihua Wang

期刊/Journal：微电子学 Microelectronics

年份/Issue Date：2013.Feb.

卷（期）及页码/Volume（No.）&pages：Vol.43, No.1

摘要/Abstract：
SRAM编译器一般需要配置具有各种字宽、各种容量的SRAM。针对这种需求，SRAM阵列和外围电路需要设计成具有可配置性、可复用性的结构。本文中使用0.525um2 6管存储单元，采用阵列划分、两级译码和具有本地时序的灵敏放大器，实现了适用于编译器的高速SRAM设计。基于SMIC 65nm CMOS工艺，对512K bits的SRAM进行了投片验证。测试结果表明：该SRAM在1.2V工作电压下可实现1.06 ns的高速访问时间。
SRAM compiler needs to configure SRAM of various word widths and sizes. To meet this need, SRAM array and periphery circuits should be designed as configurable and reusable. In this paper, array partition, two-stage decoder and sense amplifier with local timing control based on 0.525um2 6T SRAM cell were applied to achieve high-speed SRAM design for compiler. 512K bits SRAM was verified based on SMIC 65nm CMOS process. 1.12 ns high-speed access time has been achieved as the test result shown.