题目/Title：通用嵌入式SRAM IP核编译器研究与实现
                        Flexible Embedded SRAM IP Compiler Design Methodology Research and Implementation

作者/Author：王聪,刘鸣,陈虹,郑翔,曹华敏,高志强
                        Cong Wang,Ming Liu,Hong Chen,Xiang Zheng,Huamin Cao,Zhiqiang Gao

期刊/Journal：微电子学 Microelectronics

年份/Issue Date：2013

卷（期）及页码/Volume（No.）&pages：Vol.43, No.1

摘要/Abstract：
本文介绍了一种可适用于多种厂商、工艺和电路结构的嵌入式SRAM IP核编译器设计方法，该方法使编译器的设计复杂度降低了三倍以上。专用版图处理工具LayoutBuilder能自动完成版图拼接、打孔、画线、添加端口和生成GDSII版图文件等功能。专用网表处理工具NetlistBuilder仅用三个函数函数即可完成网表的生成，同时该工具还内嵌有自动检查端口数目和对齐方式功能、自动检查内部浮空节点功能和自动检查浮空端口功能。本文还介绍了一种编译器验证流程和时序与功耗文件的生成方法。我们用这个方法开发了针对2种工艺
This paper presents a novel SRAM IP compiler design methodology that greatly decreases compiler design time and complexity. When designing a new compiler, designers only need to update algorithm written in high level functions and leave rest work to specialized tools which are developed to handle foundry, technology or certain circuit structure relevant information. A new compiler verification approach based on statistics and a Synopsys technology library generating approach based on simulation and interpolation are also discussed in this paper.