题目/Title：A 14-bit Pipelined ADC with Digital Background Nonlinearity Calibration

作者/Author：李玮韬,孙操,李福乐,王志华
                        Weitao Li,Cao Sun,Fule Li,Zhihua Wang

会议/Conference：ISCAS 2013

地点/Location：Beijing, China

年份/Issue Date：2013.19-23 May

页码/pages：pp. 2448 - 2451

摘要/Abstract：
A digital background calibration algorithm is proposed to overcome nonlinearity caused by finite opamp gain and capacitor mismatch in pipelined analog-to-digital converter (ADC). The scheme, code frequency statistics (CFS), does not modify the classic pipelined stage, needs none of extra testing signals, and reduces the linearity requirement of the analog circuit. CFS is suitable for generic input and the cost of hardware is low. An experimental 14-bit pipelined ADC is fabricated to verify CFS. At 15MS/s, the measurement results show that INL errors drop from 90LSB to 0.8 LSB，SNDR grows from 38.6 dB to 66.7 dB, THD drops from -37.3dB to -82.8dB, and SFDR grows from 41.6 dBc to 86.1 dBc. The linearity of the pipelined ADC is improved significantly.