题目/Title：一种低功耗图像压缩芯片设计与实现
                        The Implementation of A Low-power and Low-area JPEG Compressor

作者/Author：刘守浩,谷荧柯,谢翔,李国林,童凯,李晓萌
                        Shouhao Liu,Yingke Gu,Xiang Xie,Guolin Li,Kai Tong,Xiaomeng Li

期刊/Journal：微电子学 Microelectronics

年份/Issue Date：2012

卷（期）及页码/Volume（No.）&pages：

摘要/Abstract：
本文设计实现了一款低功耗小面积的JPEG图像压缩芯片。该压缩芯片采用4x4分块方式，每个4x4块的一维DCT运算只需要一次乘法。二维DCT中间转置结构采用了一种新颖的实现方式，与传统的实现方式对比降低了37.5%的延时和51%的面积。该芯片经过UMC18工艺流片实现，芯片的面积和功耗分别为0.46mm2和0.9mW。测试结果显示该图像压缩芯片可以在实现较高压缩比（大于80%）的同时获得较好的图像质量（PSNR大于30dB）。
The paper presents a hardware implementation of a low-power and low-area JPEG (Joint Photographic Experts Group) compressor. The compressor uses a 4x4 divided-block to reduce the hardware complexity. The 4x4 compressor employs an optimized 1D-DCT algorithm, which contains only one multiplication. A new controlling architecture with 16 registers is used in transition buffer of 2D-DCT which reduces 37.5% latency and 51% area compared with traditional transposition architecture (two RAMs architecture). Apply similar new controlling architecture with 16 registers in zigzag buffer, 67.5% latency and 51% area can be reduced. The test result of several color images shows that high compression ratio (over 80%) can be achieved with high quality image reconstruction (PSNR over 30 dB). This JPEG compressor is carried out in 0.18 um CMOS technology. The area and power consumption of the designed compressor are 0.46 mm2 and 0.9mW, respectively.