题目/Title：A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS

作者/Author：
                        Guohe Yin,He-Gong Wei,U-Fat Chio,Sai-Weng Sin,U. Seng-Pan,Zhihua Wang,R.P. Martins

会议/Conference：ESSCIRC 2012

地点/Location：Bordeaux, France

年份/Issue Date：2012.17-21 Sept.

页码/pages：pp. 377 - 380

摘要/Abstract：
This paper presents a Successive Approximation Register Analog-to-Digital Converter (SAR ADC) design for sensor applications. An energy-saving switching technique is proposed to achieve ultra low power consumption. The measured Signal-to-Noise-and-Distortion Ratio (SNDR) of the ADC is 58.4 dB at 2 MS/s with an ultra-low power consumption of only 6.6 μW from a 0.8V supply, resulting in a Figure-Of-Merit (FOM) of 4.9 fJ/conversion-step. The prototype is fabricated in 65 nm CMOS technology with an area of 0.024 mm2.