题目/Title：A 12-bit 110MS/s 4-stage Single-Opamp Pipelined SAR ADC with Ratio-Based GEC Technique

作者/Author：王睿,赵汝法,冼世荣,余成斌,王志华,马许愿
                        Rui Wang,U-Fat Chio,Sai-Weng Sin,U. Seng-Pan,Zhihua Wang,R.P. Martins

会议/Conference：ESSCIRC 2012

地点/Location：Bordeaux, France

年份/Issue Date：2012.17-21 Sept.

页码/pages：pp. 265 - 268

摘要/Abstract：
This paper presents a 12-bit 110MS/s 4-stage pipelined SAR ADC integrated through a single low-gain op-amp. A ratio-based GEC (Gain Error Calibration) technique based on op-amp sharing is proposed to reduce the complexity of digital calibration circuit. Only one PN (Pseudo-random Number) signal is employed to perform the dither injection but calibrate multiple gain errors, and thus accelerates the convergence speed, gets rid of input signal reduction and minimizes the analog modification due to the background calibration. The effectiveness of the architecture is verified in 65-nm CMOS chips whose analog core area is 0.12 mm2 only. The ADC obtains an average SNDR of 63 dB and SFDR of 75.2 dB at 110MS/s consuming analog power of 11.5mW from a 1.2-V supply. Only 40 thousand points are needed to achieve desirable SNDR with the proposed calibration technique.