题目/Title：A 512 kb SRAM in 65nm CMOS with Divided Bitline and Novel Two-stage Sensing Technique

作者/Author：郑翔,刘鸣,陈虹,曹华敏,王聪,高志强
                        Xiang Zheng,Ming Liu,Hong Chen,Huamin Cao,Cong Wang,Zhiqiang Gao

会议/Conference：DDECS 2012

地点/Location：Tallinn, Estonia

年份/Issue Date：2012.18-20 April

页码/pages：pp. 191 - 192

摘要/Abstract：
This paper focuses on high speed embedded SRAM design, especially on novel circuit technique to improve SRAM access time. A new two-stage sensing scheme which is able to reduce long interconnection metal line delay by transferring differential signals with half swing amplitude has been proposed. Post-layout simulation results show that the long distance signal transmission time has been decreased by 45%. Chip measurement shows the access time has been decreased by 23% at the expense of little area penalty (1.3%) and some read power penalty (about 16%) mainly caused by 2nd-stage sense amplifiers.