题目/Title：Semidigital PLL design for low-cost low-power clock generation

作者/Author：
                        Ni Xu,Woogeun Rhee,Zhihua Wang

期刊/Journal：Journal of Electrical and Computer Engineering

年份/Issue Date：2011Sept.

卷（期）及页码/Volume（No.）&pages：Vol.2011, pp. 1 - 9

摘要/Abstract：
This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature. Two design examples in 0.18 μm CMOS and 65 nm CMOS are presented with hardware and simulation results, respectively.