题目/Title：Technology-Friendly Phase-Locked Loops

作者/Author：徐妮,张卓,孙远峰,李宇根,王志华
                        Ni Xu,Zhuo Zhang,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang

会议/Conference：MWSCAS 2011

地点/Location：Seoul, Korea

年份/Issue Date：2011.7-10 Aug.

页码/pages：pp. 1 - 4

摘要/Abstract：
This paper presents recent architectures of the phaselocked loop (PLL) systems which relax technology dependency and provide robust, low-cost frequency generation. The first partof the paper discusses architecture advantages of the dual-path PLL which significantly reduces loop bandwidth variation. Thesecond part of the paper reviews recent hybrid PLL architectures which do not employ the time-to-digital converter (TDC) but still offer technology scalability and leakage current immunity.