题目/Title：Low-Noise Fractional-N PLL Design with Mixed-Mode Triple-Input LC VCO in 65nm CMOS

作者/Author：
                        Yuanfeng Sun,Xueyi Yu,Woogeun Rhee,Sangsoo Ko,Wooseung Choo,Byeong-Ha Park,Zhihua Wang

会议/Conference：RFIC 2010

地点/Location：Anaheim, CA

年份/Issue Date：2010.23-25 May

页码/pages：pp. 61 - 64

摘要/Abstract：
This paper describes a low-noise ΔΣ fractional-NPLL utilizing a mixed-mode triple-input LC VCO. An analogdual-path VCO control relaxes the nonlinearity problem of theΔΣ fractional-N PLL, while a combination of discrete andcontinuous tuning methods for the coarse-tuning controlsignificantly alleviates noise and coupling problems caused by ahigh coarse-tuning control path. A 3.6GHz ΔΣ fractional-N PLLimplemented in 65nm CMOS exhibits nearly –100dBc/Hz inbandnoise contribution and –75dBc fractional spurperformance at 500kHz offset frequency from a 1.8GHz carrier.