题目/Title：
                        A 13-bit, 8 MSample/s Pipeline A/D Converter

作者/Author：郭丹丹,李福乐,张春,王志华
                        Dandan Guo,Fule Li,Chun Zhang,Zhihua Wang

期刊/Journal：半导体学报 Chinese Journal of Semiconductors

年份/Issue Date：2009

卷（期）及页码/Volume（No.）&pages：Vol.30, No.2, pp. 0250061 - 5

摘要/Abstract：

A 13-bit 8MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-and-hold amplifier (SHA) is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers (opamps) are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in a 0.18-μm 1P6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 dB and 91.6 dB at 2.5MSample/s, 74.3 dB and 85.4 dB at 8.0MSample/s. It consumes 8.1mW, 21.6mW, 29.7mW and 56.7mW (including I/O drivers) when operating at 1.5MSample/s, 2.5MSample/s, 5.0MSample/s and 8.0MSample/s at 2.7 V power supply, respectively. The chip occupies 3.2 mm2, including I/O pads.