题目/Title：A 65nm CMOS 3.6GHz fractional-N PLL with 5th-order ΔΣ modulation and weighted FIR filtering

作者/Author：
                        Xueyi Yu,Yuanfeng Sun,Woogeun Rhee,Sangsoo Ko,Wooseung Choo,Byeong-Ha Park,Zhihua Wang

会议/Conference：A-SSCC 2009

地点/Location：Taipei

年份/Issue Date：2009.16-18 Nov.

页码/pages：pp. 77 - 80

摘要/Abstract：
A 3.6 GHz fractional-N PLL utilizing high-order digital modulation and weighted 13-tap finite impulse response (FIR) filtering for low spur and enhanced noise reduction is implemented in 65 nm CMOS. The prototype PLL exhibits nearly -100 dBc/Hz in-band noise contribution and -126.8 dBc/Hz phase noise at a 3 MHz offset from a 1.8 GHz carrier. With 5th-order single-loop ΔΣ modulation, the fractional spur levels of -65.6 dBc and -58.5 dBc are achieved within the bandwidth and near the bandwidth, respectively.