题目/Title：用于数据转换器的时钟合成器设计
                        Design of CMOS Clock Synthesizer for Data Converters

作者/Author：杨跃进,李国林
                        Yuejin Yang,Guolin Li

期刊/Journal：微电子学 Microelectronics

年份/Issue Date：2008.Oct.

卷（期）及页码/Volume（No.）&pages：Vol.38, No.5, pp. 740 - 747

摘要/Abstract：
设计了一种用于数据转换器的低抖动锁相环时钟合成器.基于一阶锁相环结构,提出新的系统分析线性模型,改进了片上无源离散环路滤波器,大大缩短了设计周期.该21.88 MHz时钟合成器采用0.18 μm CMOS混合信号工艺,在1.8 V电源电压下,电荷泵和压控振荡器功耗为410 μA.时钟合成器在1 MHz频偏处相位噪声为-114 dBc/Hz.
A CMOS PLL clock synthesizer for ADC clock applications was designed．Based on Type I PLL architecture，a new linear model for system-level analysis was presented，and an improved on-chip passive discrete-time loop filter was proposed，which drastically shorten time-to-market. The 21.88 MHz clock synthesizer demonstrator test chip has been fabricated in a mixed-signal 0.18um CMOS process．The charge pump and VCD core on the chip consume 410uA of power from a 1.8-V supply．The synthesizer has a phase noise of -114 dBc/Hz at 1MHz offset.