题目/Title：一种900MHz RFID读卡器中的高性能CMOS频率综合器
                        CMOS Implementation of an RF PLL Synthesizer for Use in RFID Systems

作者/Author：谢维夫,李永明,张春,王志华
                        Weifu Xie,Yongmin Li,Chun Zhang,Zhihua Wang

期刊/Journal：半导体学报 Chinese Journal of Semiconductors

年份/Issue Date：2008

卷（期）及页码/Volume（No.）&pages：Vol.29, No.8, pp. 1595 - 1601

摘要/Abstract：
实现了一个应用于RFID系统的低功耗、低噪声的锁相环频率综合器.该频率综合器采用UMC 0.18μm CMOS工艺实现,输入时钟为13MHz,经测试验证输出频率为718~915MHz,相位噪声为-124dBc/1MHz,-101.13dBc/100kHz,频率分辨率为200kHz,功耗为54mW.
An integrated RF PLL frequency synthesizer for use in RFID systems is presented.It integrates a voltage-controlled oscillator,phase frequency detector,charge pump,high-frequency dual-modulus divider,and digital programmable divider.The frequency synthesizer was implemented in a 0.18μm CMOS process.It uses a 13MHz crystal oscillator as input.The output range is from 860 to 960MHz,the phase margin is-123dBc/1MHz,the frequency step is 200kHz,and the change frequency is within 150μs.