题目/Title：Full custom design of a three-stage amplifier with 5500MHz•pF/mW Performance in 0.18 μm CMOS

作者/Author：
                        Run Chen,Liyuan Liu,Dongmei Li,Zhihua Wang

会议/Conference：VLSI-SoC 2007

地点/Location：Atlanta, GA, USA

年份/Issue Date：2007.15-17 Oct.

页码/pages：pp. 242 - 247

摘要/Abstract：
A full custom design of a three-stage amplifier is described in this paper. A feedback transconductance stage and a feedforward stage combined with two Miller compensation capacitors are used for frequency compensation. The circuit is designed in 0.18μm CMOS process with a 1.8V supply voltage. When driving a 150pF capacitive load, the amplifier achieves over l00dB de gain, 2.24MHz gain- bandwidth product (GBW), 62° phase margin (PM), 1.2V/μs slew rate (SR) and 61μW power dissipation. Compared to conventional multistage amplifiers, this work provides improvement in both GBW and SR, and also shows a significant improvement in MHz·pF/mW performance.