题目/Title：A linear voltage regulator for PLL in SOC application

作者/Author：
                        Chen Jia,Bo Qin,Zhiliang Chen

会议/Conference：WiCOM 2006

地点/Location：Wuhan, China

年份/Issue Date：2006.22-24 Sept.

页码/pages：pp. 1 - 4

摘要/Abstract：
In modern integrated circuit design, analog parts and digital parts are designed on a single chip. Many papers show that supply noises coupling from digital parts influence the performance of analog parts greatly. This paper presents a design to implement a linear voltage regulator with operational amplifiers for PLL in mixed signal integrated circuits, whose output voltage is proportional to bandgap reference. This circuit is designed in SMIC 0.18 mum CMOS process. The output voltage of the regulator can be stable when 1) power supply changes from 3.1 V to 3.5 V, and verse; 2) output current varies in the range from 15 mA to 300 muA. Its power supply noise rejection(PSNR) is less than -70 dB when frequency is below 1 KHz. The current consumption of this linear voltage regulator is about 1.7 mA