题目/Title：A low power VLSI implementation for JPEG2000 codec, ASICON 2005

作者/Author：
                        Yicong Meng,Leibo Liu,Li Zhang,Zhihua Wang

会议/Conference：ASICON 2005

地点/Location：Shanghai, China

年份/Issue Date：2005.24-27 Oct.

页码/pages：pp. 198 - 202

摘要/Abstract：
This paper proposed a low power VLSI implementation of JPEG2000 codec. Three power optimization schemes including gated clock, bus-invert and dual voltage scaling are adopted. An automated design flow for dual voltage scaling is also proposed. The JPEG2000 codec was fabricated in SMIC 0.18μm 1P6M standard CMOS technology. And it is capable of JPEG2000 compression/decompression with a 1280×1024 pixel (YUV422 full color) at 20frames/s employing a 100MHz operating frequency. The power consumption is reduced by 54% and is 465mW @ 1.8V and 100 MHz.