题目/Title：A VLSI architecture of JPEG2000 encoder

作者/Author：
                        Liu, Leibo,Ning Chen,Hongying Meng,Li Zhang,Zhihua Wang,Hongyi Chen

期刊/Journal：IEEE Journal of Solid-State Circuits

年份/Issue Date：2004Nov.

卷（期）及页码/Volume（No.）&pages：Vol.39, No.11, pp. 2032 - 2040

摘要/Abstract：
This paper proposes a VLSI architecture of JPEG2000 encoder, which functionally consists of two parts: discrete wavelet transform (DWT) and embedded block coding with optimized truncation (EBCOT). For DWT, a spatial combinative lifting algorithm (SCLA)-based scheme with both 5/3 reversible and 9/7 irreversible filters is adopted to reduce 50% and 42% multiplication computations, respectively, compared with the conventional lifting-based implementation (LBI). For EBCOT, a dynamic memory control (DMC) strategy of Tier-1 encoding is adopted to reduce 60% scale of the on-chip wavelet coefficient storage and a subband parallel-processing method is employed to speed up the EBCOT context formation (CF) process; an architecture of Tier-2 encoding is presented to reduce the scale of on-chip bitstream buffering from full-tile size down to three-code-block size and considerably eliminate the iterations of the rate-distortion (RD) truncation.