Title：Front-end circuit for analogue-to-digital converter with pipeline structure and time sequence control method thereof
Country：China
Patent No.：201310146910.6
Legal Status：Authorized
Inventor：Fule Li, Chun Zhang, Zhihua Wang
Assignee：Tsinghua University
Address：Institute of microelectronics, Tsinghua University, Haidian District, Beijing 100084
Filing Date：2013-04-25
Issue Date：2017-03-15
Abstract：
The invention discloses a front-end circuit for an analogue-to-digital converter with a pipeline structure and a time sequence control method for the front-end circuit, and aims to eliminate a sampling and holding amplifier, improve power consumption and noise indexes and reduce conversion delay. The front-end circuit is used for realizing the analogue-to-digital conversion of M1+M2 bits, and acquiring a second analogue residual error signal, wherein the second analogue residual error signal is used for the sampling of the next conversion stage of the front-end circuit in the analogue-to-digital converter with the pipeline structure. The front-end circuit comprises a first conversion stage and a second conversion stage, wherein the first conversion stage is used for directly sampling an input signal to finish the analogue-to-digital conversion of M1 bits, and acquiring a first analogue residual error signal; and the second conversion stage is used for receiving and sampling the first analogue residual error signal to finish the analogue-to-digital conversion of M2 bits, and acquiring the second analogue residual error signal.
Patent Certificate：
PDF/Jpg