Title：A voltage buffer for high-speed ADC

Country：China

Patent No.：201110223250.8

Legal Status：Authorized

Inventor：Libing Zhou, Liyuan Liu, Dongmei Li

Assignee：Tsinghua University

Address：Tsinghua University,Haidian District Beijing 100084, China

Filing Date：2011-08-05

Issue Date：2013-12-11

The invention relates to a voltage buffer applied to a high-speed analogue-to-digital converter, and belongs to the field of mixed signal integrated circuit designing. The voltage buffer comprises three P-channel metal oxide semiconductor (PMOS) transistor and three N-channel metal oxide semiconductor (NMOS) transistors. Connection relationships among the MOS transistors are that: the drain and gate of a first NMOS transistor are connected together and connected to the gate of the second PMOS transistor and the drain of the first PMOS transistor; a positive reference input voltage is connected to the gate of the first PMOS transistor after passing through a bonding wire; the source of the first PMOS transistor and the drain of the second PMOS transistor are connected together; the sources of the second and third PMOS transistors are connected together and finally connected to an external power potential after passing through the bonding wire; the drain and gate of the third PMOS transistor are connected together and connected to the gate of the third NMOS transistor and the drain of the second NMOS transistor; a negative reference input voltage is connected to the gate of the second NMOS transistor after passing through the bonding wire; the source of the second NMOS transistor and the drain of the third NMOS transistor are connected together; and the sources of the first and third NMOS transistors are connected together and finally connected to an external ground potential after passing through the bonding wire. The voltage buffer has the characteristics of higher charging speed and reference voltage capable of reaching rated accuracy faster.

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