Biography
Enrollment Date: 2014
Graduation Date：2017
Degree：M.S.
Defense Date：2017.05.25
Advisors：Chun Zhang
Department：Graduate School at Shenzhen，Tsinghua University
Title of Dissertation/Thesis：Design of High-speed Solid State Drive in FPGA
Abstract:
With the development of technology and Internet, the cloud storage and big data industry growth explosionly. They have higher requirement to storage device on security, reliability. The invention of 3D NAND flash give the storage industry the second life. Nowadays, the max speed of NAND Flash is upon to 800MT/s and the max speed of SATA is just 600MB/s. The SATA bus interface become the bottleneck for SSD. PCIE bus interface is connected directly to CPU. The higher bandwidth and fast speed of PCIE make it the new choice for SSD designer.At present, the realization of SSD mainly based on ASIC and FPGA. The FPGA is flexible and can be programmed repeatly. We can easily upgrade the new ECC algorithm, interface protocol and data security algorithms in FPGA.In this paper, the solid-state drive with PCIE3.0 bus interface is designed and implemented. The main contents of the work include three parts. First, the design of NAND flash memory chip interface controller. The flash controller obeys the design rule of ONFI protocol. It supports SDR and DDR two transmission modules, the maximum transmission speed can reach 200MT / s. Second, configure the PCIE hard core for the 4-channel PCIE3.0 mode. The maximum transmission speed is around 1500MB / s in the real test. The Linux PCI driver is also programmed for test. Third, the design of SSD structure contains several part: the MICROBLAZE soft core, PCIE sub-module, DMA module, NAND flash controller module. The design sperates the data stream and control stream. The dual bus has a big advantage in area reduction and in clock frequency improvement. The firmware is programed on the MICROBLAZE soft IP core to cope with host event.To test the SSD controller, a hardware test platform is built. The host and FPGA development boards are connected by PCIE card slots, and the FPGA development board and NAND FLASH child board are connected via FMC. Read and write functional test scripts and write speed test scripts is executed on the host and start test.