题目/Title：
                        A 40 Gb/s SerDes Transceiver Chip with Controller and PHY in a 65nm CMOS Technology

作者/Author：吕方旭,王建业,郑旭强,王自强,贺娅君,丁浩,刘勇聪,张春,王志华
                        Fangxu Lv,Jianye Wang,Xuqiang Zheng,Ziqiang Wang,Yajun He,Hao Ding,Yongcong Liu,Chun Zhang,Zhihua Wang

期刊/Journal：哈尔滨工业大学学报(新系列) Journal of Harbin Institute of Technology (New Series)

年份/Issue Date：2019.May

卷（期）及页码/Volume（No.）&pages：Vol.26, No.3, pp. 50-57

摘要/Abstract：

A 40 Gb/s full serializer and deserializer（SerDes） transceiver with controller and physical layer（PHY） is presented. The controller mainly contains protocol transmission, forward error correction and user layer build-in self-test（BIST）. The physical coding sub-layer（PCS） provides the functions of 64/66 encoder/decoder, PHY BIST, and polarity control. In the physical medium attachment（PMA）, both transmitter（TX） and receiver（RX） adopt quarter-rate architecture to relax the timing constraint and reduce power dissipation. The receiver utilizes the phase interpolator（PI） based clock and data recovery（CDR） with bang-bang phase detector（BBPD） to extract the synchronic clock for retiming and de-multiplexing. The multiple-MUX based 4-tap FFE and a two-stage cascade CTLE are employed to mitigate the inter-symbol interference（ISI）. In addition, a proposed 4∶1 MUX is used to improve the output jitter performance and reduce the power consumption. Fabricated in a 65 nm CMOS technology, the full transceiver consumes 890 mW at 40 Gb/s and occupies 12 mm2. The measurement results show that this transceiver can achieve bit error rate（BER） < 10-12 after a 15.3 dB loss channel at 20 GHz.