题目/Title：High performance low complexity BCH error correction circuit for SSD controllers

作者/Author：
                        Ping Chen,Chun Zhang,Hanjun Jiang,Zhihua Wang,Shigang Yue

会议/Conference：EDSSC 2015

地点/Location：Singapore

年份/Issue Date：2015.1-4 Jun.

页码/pages：pp. 217 - 220

摘要/Abstract：
This paper presents an Error Correction Code (ECC) module circuit for Solid State Drive (SSD) controllers by Bose-Chaudhuri-Hocquenghem (BCH) code. 32-bit parallel architecture was used to design the encoder, while 2-stage pipeline structure was applied to complete the decoder. In addition, re-encoding, simple inversion-free Berlekamp-Massey (SiBM) algorithm and sharing common-sub-expressions (CSEs) were all introduced to lower hardware complexity. FPGA verification results showed that this BCH (9193, 8192, 72) circuit can realize maximum error correction capability as 72bit/lKB. Moreover, the circuit's data throughput can reach 3.2 Gbps and it will occupy 119.5K logic gate counts using 65nm technology.