题目/Title：A 4.8-mW/Gb/s 9.6-Gb/s 5+1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS

作者/Author：袁帅,王自强,郑旭强,黄柯,徐妮,李宇根,乌力吉,张春
                        Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Ke Huang,Ni Xu,Woogeun Rhee,Liji Wu,Chun Zhang

期刊/Journal：IEEE Transactions on Circuits and Systems II: Express Briefs

年份/Issue Date：2014

卷（期）及页码/Volume（No.）&pages：Vol.61, No.4, pp. 209 - 213

摘要/Abstract：
A low-jitter and low-power source-synchronous serializer/deserializer transmitter (TX) with a data rate of 9.6 Gb/s is presented. The TX consists of five data channels plus one forwarded-clock channel and features a total jitter of 20.39 ps p-p at 10−12 bit error rate. Low jitter is achieved through the use of a phase-locked loop with bandwidth linearization that has a random RMS jitter of 0.66 ps. A global clock distribution network is proposed to minimize the power-supply-induced jitter and the power consumption. The TX transmits preemphasized data through a current-mode logic driver with a four-tap feedforward equalizer. The on-chip output impedance and the signal amplitude can be accurately calibrated by a successive approximation register logic separately. The total power consumption for the 5 + 1-lane TX physical core fabricated in 65-nm bulk CMOS running at 9.6 Gb/s is 230 mW or 4.8 mW/Gb/s.