题目/Title：A 12bit 100MSps Pipelined ADC without Calibration

作者/Author：蔡小波,李福乐,李玮韬,张春,王志华
                        Xiaobo Cai,Fule Li,Weitao Li,Chun Zhang,Zhihua Wang

会议/Conference：CISP 2010

地点/Location：Yantai

年份/Issue Date：2010.16-18 Oct.

页码/pages：pp. 3547 - 3552

摘要/Abstract：
A 1.8V 12bit 100MS/s pipelined ADC in 0.18um CMOS process is presented. The first stage adopts 3.5-bit structure to relax the capacitor matching requirements. Bootstrapped switch and scaling down technique are used to improve the ADC's linearity and save power dissipation respectively. With a 2.4 MHz input signal, the ADC achieves 68.9dB SFDR and 9.3 ENOB at 101MS/s. The power consumption is 180mW at 1.8V supply including output drivers. The chip area is 3.51 mm2 including pads.