题目/Title：基于动态元件匹配技术的改进逐次逼近ADC设计
                        An enhanced Successive Approximation ADC based on Dynamic Element Matching Technique

作者/Author：古松,李冬梅
                        Song Gu,Dongmei Li

期刊/Journal：半导体技术 Semiconductor Technology

年份/Issue Date：2009

卷（期）及页码/Volume（No.）&pages：Vol.34, No.9, pp. 907 - 911

摘要/Abstract：
本文介绍了一种低功耗、中等速度、中等精度的改进逐次逼近ADC，用于DSP的外围接口中。其中DAC采用分段电容阵列结构，节省了芯片面积，其高三位使用了动态元件匹配技术，改善了ADC的性能。比较器采用四级预放大器和Latch串联构成，并且使用了失调校准技术。数字电路采用全定制设计，辅助模拟电路完成逐次逼近过程，并且能够使ADC进入省电模式。芯片使用UMC 0.18m 混合信号CMOS工艺制造，版图面积2.2mm×1.5mm。后仿真结果显示，ADC可以在1.8V电压下达到12bit精度，速度1M
A low-power, medium-speed and medium-resolution enhanced successive approximation ADC is described, which is used as an interface of DSP. Its DAC adopts a split capacitive array in order to lower chip size, which uses dynamic element matching technique in the most three significance bits so as to improve the ADC performance. Four pre-amplifiers and a latch consist of the comparator, and offset cancellation technique is employed. The digital logic part is full-custom designed, which coordinates the analog circuits to accomplish successive approximation and can power down the whole ADC. The chip is fabricated in UMC 0.18m Mixed Mode CMOS technology, the layout occupies an area of 2.2mm×1.5mm. The post-simulation results show that, the ADC achieves 12bit at 1MSps sampling rate and consumes only 2.6mW power using a 1.8V Supply voltage.