题目/Title：一种高线性度100kHz带宽的ΣΔ调制器
                        A high linearity 100kHz signal bandwidth ΣΔ modulator

作者/Author：朱颖佳,刘力源,李冬梅
                        Yingjia Zhu,Liyuan Liu,Dongmei Li

期刊/Journal：微电子学 Microelectronics

年份/Issue Date：2009

卷（期）及页码/Volume（No.）&pages：Vol.39, No.5, pp. 610 - 614

摘要/Abstract：
ΣΔ-A/D具有对工艺偏差不敏感、与VLSI技术兼容性好、实现精度高、灵活性强的特点。本论文设计一个100kHz信号带宽，80dB SNDR，3.3V电源电压的单环三阶ΣΔ调制器。调制器采用AB类运放，可在较低的静态功耗下实现较高的压摆率。该设计采用UMC 0.18um CMOS工艺，版图面积为1.7mm×1.3mm。芯片测试结果为：在12MHz时钟频率，60倍过采样的情况下，调制器可以达到100 kHz信号带宽，75.7dB SNDR以及98dB SFDR。
ΣΔ-A/D is insensitive to fabrication and compatible with today’s VLSI technology. It can also reach high resolution and flexibility. This paper shows the whole design of a single-loop 3rd-order ΣΔ modulator for 80dB SNDR 100kHz signal bandwidth applications with 3.3V power supply. The modulator uses class AB OTA to meet the requirement of high slew rate with relatively low static power dissipation. The chip is fabricated in UMC 0.18um CMOS technology. With an oversampling ratio of 60 and a clock rate of 12 MHz, the modulator achieves a 75.7 dB SNDR and 98dB SFDR in chip measurement. The whole chip size including PADs is 1.7mm*1.3mm.