题目/Title：A Low Power, Fully Pipelined JPEG-LS Encoder for Lossless Image Compression

作者/Author：
                        Xiaowen Li,Xinkai Chen,Xiang Xie,Guolin Li,Li Zhang,Chun Zhang,Zhihua Wang

会议/Conference：ICME 2007

地点/Location：Beijing

年份/Issue Date：2007.2-5 July

页码/pages：pp. 1906 - 1909

摘要/Abstract：
By analyzing the features unfit for parallel computation and low power implementation, a VLSI architecture of JPEG-LS encoder for lossless image compression is proposed in this paper. It functionally consists of four parts: Mode decision module, clock controller, three linear parallel pipelines, and a two-tier data packer. Computations are organized in a fully pipelined style in these modules, so that real time data processing can be achieved. The clock management scheme with four interlaced clock domains and a dedicated clock controller is applied to ensure the bottleneck calculation, reduce the clock frequency on non-critical paths, and shut off the working clocks of idle modules, which reduces 15.7% of overall power consumption. The proposed JPEG-LS encoder with the features of low power and high processing speed, has been applied in a wireless endoscopy system.