题目/Title：低功耗13b 10^7样品/s模数转换器
                        Low power 13bit 10^7 sample/s A/D converter

作者/Author：李福乐,王红梅,李冬梅,王志华
                        Fule Li,Hongmei Wang,Dongmei Li,Zhihua Wang

期刊/Journal：清华大学学报（自然科学版） Journal of Tsinghua University (Science and Technology)

年份/Issue Date：2006.Jan.

卷（期）及页码/Volume（No.）&pages：Vol.46, No.1, pp. 115 - 118

摘要/Abstract：
描述一个基于0.6μm CMOS工艺的、低功耗的13b,10^7样品/s流水线模数转换器(ADC)的设计。为了达到13b的转换精度,在电路设计中采用了电容误差平均技术；为了实现低功耗设计,在电路设计中综合采用了运算放大器共享、输入采样保持放大器消去、按比例缩小和动态比较器等技术。在考虑工艺实现中的非理想因素的条件下,对ADC电路进行晶体管级Monte-Carlo仿真,当ADC以10MHz的采样率对1MHz的正弦输入信号进行采样转换时,在其输出得到了82dB的非杂散动态范围,并且此时ADC模拟部分的功耗仅为
The design of a low-power 13bit, 107sample/s pipelined analog -to-digital converter (ADC) in 0.6μm CMOS technology was described. The capacitor error averaging technique was used to achieve the 13bit precision, with circuit techniques such as operational amplifier sharing, input sample-and-hold amplifier cancellation, and dynamic comparator used to reduce the power. Technology non-idealities were included in a transistor-level Monte-Carlo simulation of the ADC. Simulation results show that a free dynamic range of 82dB is achieved for an input of 1MHz at a full speed of 10MHz while consuming only 11mW of power in the analog section.