题目/Title：A 128 Gbps PAM-4 feed forward equaliser with optimized 1UI pulse generator in 65 nm CMOS

作者/Author：
                        Jiawei Wang, Hao Xu, Ziqiang Wang, Haikun Jia, Hanjun Jiang, Chun Zhang, Zhihua Wang

期刊/Journal：IET CIRCUITS DEVICES & SYSTEMS

年份/Issue Date：2023Feb.

卷（期）及页码/Volume（No.）&pages：Vol.17, No.3, pp.174-179

摘要/Abstract：

A quarter-rate PAM-4 FFE employing INCC 1UIPG is implemented in 65 nm CMOS. The proposed INNC 1UIPG reduces the average transition time by ~20%, saving clocking power consumption by ~1.5X, lowering jitter amplification by about 2~5 dB compared with previous works. Along with the bandwidth- and power-efficient partially segmented tailless 1-stage front-end architecture, the proposed FFE achieves 128Gbps PAM-4 data rate with a 0.014 mm2 area.